Micro-Electro-Mechanical Systems or MEMS are typically the integration of mechanical elements, sensors, actuators and electronics on a common silicon substrate such as a wafer through the utilization of micro-fabrication technologies. MEMS are envisaged to revolutionise nearly every micro-device product category by bringing together silicon-based microelectronics with micromachining technologies. In this way, MEMS make possible the realisation of the concept of complete systems-on-a-chip. Hence, the commercial potential of MEMS devices is practically boundless in the current marketplace.
However, extensive MEMS commercialisation is currently hampered due to the attendant difficulties of packaging these micro-devices and the high cost involved in packaging and testing the micro-devices. The cost of packaging and testing such micro-devices can be up to ten times more expensive than the cost of manufacturing the micro-devices. The much sought after technological breakthrough that is anticipated to drive MEMS commercialisation is packaging technologies for MEMS. This is because the process of packaging MEMS affects not only the micro-device size and cost, but also is the most unreliable step and the bottleneck in achieving high performance for MEMS. For the successful commercialisation of the highly innovative MEMS devices, the importance of MEMS packaging and conjunctively used carriers must be addressed and realised at the early design cycles of MEMS.
Although MEMS fabrication technologies apply a number of processes similar to integrated circuit (IC) fabrication technologies, MEMS packaging technologies are substantially different and more challenging than IC packaging technologies. MEMS packaging technologies need to satisfy a number of requirements relating to adequate mechanical protection for moving structures and thin membranes in the MEMS devices from environmental contamination, vibration and etc; interaction with environment for sensing and actuating; support for electrical power and signals such as low lead inductance, capacitance and resistance; good heat dissipation; manufacturability suitable for integration into Wafer-Level Packaging (WLP) processes; reliability; and economical or cost effective.
The reliability of MEMS depends on packaging type, materials, wafer-level processes and sealing methods used for environmental protection employing micro-device caps or microcaps. The development process of MEMS package and packaging process is the single most expensive and time-consuming process in the entire MEMS product development cycle. This difficulty stems from the fact that MEMS packaging is typically applied to Application Specific MEMS Packages (ASMP), thus making MEMS packaging difficult to develop for generic applications.
Currently, most development efforts for MEMS packaging result in new and specialised packaging every time a new MEMS device is fabricated. Even the packaging of one of most popular mass-produced MEMS devices, the accelerometer, involves specific packaging strategies that are dependent on different manufacturers.
Thus, generic and modular ways of designing MEMS packaging are desirable and can significantly reduce the total cost of MEMS as well as save time and effort during early design cycles for MEMS. However, it is often easy to neglect considering the packaging aspect of MEMS fabrication when designing MEMS devices. The packaging strategy for MEMS, however, must be considered right from the beginning of the product development and fabrication of MEMS. For most MEMS devices, hermetic packaging is the desired form of packaging. Perfect hermetic packaging has good reliability, but achieving this ideal requisite is very expensive and challenging.
A number of MEMS packages are currently fabricated using Wafer-Level Packaging (WLP) technologies. MEMS packages can also be chip-scale packages, which are device packages that allow devices to be attached to device carriers or printed circuit boards (PCB) face-down with the devices' pads connecting to the carriers or PCBs through individual balls of solder. WLP is a packaging technology performed at the wafer level that requires the bonding of two or more wafers before singulation or dicing of the bonded wafers to obtain the individual devices that are already packaged. WLP is a powerful concept that can bring the total production cost of micro-devices significantly down. Although each WLP processing step tends to be more costly than conventional post-singulation packaging processes, the cost is divided among all the devices on a wafer.
Typical wafer-level interconnection structures use layers of polymer dielectric systems and a thin metal film redistribution layer. Ultimately, to achieve high I/O density, electrical power distribution by using through-wafer vias is necessary, especially for space-efficient applications. The wire bonding technique is a popular technique for providing electrical interconnection, such as that employed in a conventional MEMS device 1 shown in FIG. 1A, in which a MEMS wafer 2 is bonded to a cap wafer 3 and a MEMS device 4 on the MEMS wafer 2 is connected to a solder ball 5 through a wire bond 6 which is held in a via 7 using an epoxy material 8. The wire bonding technique has limited application in MEMS packaging. For example, ultra sonic energy applied in the frequency range between 50 and 100 kHz for performing wire bonding may stimulate the oscillation of the suspended mechanical structure of the MEMS device 4. This is because most MEMS devices have resonant frequency in the foregoing frequency range, thereby increasing the risk of failure during wire bonding.
Through-wafer vias are typically intended for providing interconnects between both sides of wafers with which micro-devices are fabricated using WLP. Current packaging trend shows that vertical interconnects are favoured because of space efficiency and design simplicity, leading to the increased popularity of WLP devices. For example, array sizes of devices for input/output (I/O) are limited when electrical connections are, found at the periphery of the devices, primarily due to limited space along the edges of the devices for I/O leads. This limitation necessitates the use of through-wafer interconnects for micro-devices.
Also, achieving low parasitic capacitance and impedance is critical for MEMS devices that are used in RF applications. Research has been conducted for making these through-wafer vias conductive with low capacitance for such RF applications. Deep-wafer etching has also been widely studied in MEMS technology because obtaining high density and high aspect ratio through-wafer vias is critical for optimising for integration and final device performance. The most two popular deep-wafer etching processes are Bosch and Cryo process.
A number of wafer-to-wafer bonding techniques have been developed for packaging micro-devices to achieve hermetic sealing. These techniques include silicon-to-glass anodic bonding, silicon-to-silicon fusion bonding, and wafer-to-wafer bonding using various intermediate materials as bonding media. Connections to a hermetically sealed micro-device are generally made under the bonding media against one of the wafers or through one of the wafer. Based on the foregoing preferences for vertical connections, through-wafer vias are thus favoured where hermetic sealing of micro-devices is an attendant requirement.
One of the solutions for MEMS packaging can be to use electrically conductive through-wafer vias. These vias can be connected to metal conductors that connect to bond pads of the MEMS device. Such vias have advantages for space improvement and efficiency, and can be fabricated in a high volume-manufacturing method using bulk micromachining. For low I/O count devices, this method can be used without difficulty. For high I/O count micro-devices, however, this option can be a technical challenge.
In U.S. Pat. No. 6,228,675 granted to Ruby et al, with reference to FIG. 1B, a method of fabricating a microcap 10 with vias 26/28 defined on a cap wafer 24 is proposed. The vias 26/28 are initially etched as trenches or wells and are filled by a conductive material from the top or the side of the cap wafer 24 having the trenches before the cap wafer 24 is bonded with a MEMS device wafer 12 to provide hermetic sealing. The cap wafer 24 is later thinned by backgrinding the non-trench side of the cap wafer 24 to expose the conductive vias 26/28. The main limitation in such a proposal is that it provides for forming conductive vias 26/28 that are made of semiconductor materials like Polysilicon, III-V materials or etc, which results in higher series resistance due to conductive vias than metallized vias. This approach only works for trenches with narrow openings (<10 um) but not for trenches with larger openings because a proportionately thicker conductive material needs to be deposited to fill-up the vias before subsequent process steps are performed. This further results in excessive material build-up that induces very high film stress in the cap wafer, from which the microcap 10 is formed, which is susceptible to breakage due to deep vias that are already formed in the cap wafer. Additionally, by such a proposed method it is not possible to fill very deep trenches, as it is very difficult to obtain a conforming semi-conductor dopant layer. From the foregoing problems, it is apparent that there is a need to provide an alternative to the conventional wafer-level packaging for micro-devices.
In an article entitled “Through-Wafer Copper Plugs Formation For 3-Dimensional ICs” by T. Nguyen et al, DIMES Netherlands, a method for forming high aspect ratio conductive through-wafer vias 202 in a wafer 204 by forming seed metal layers and applying a “bottom-up” approach for filling the through-wafer vias 202 in thin wafers is proposed. The bottom-up approach involves forming the through-wafer vias 202 and then filling these vias 202 which are blocked on one side 206 of the wafer 204 by a thin seed metal layer 208 that is deposited by an evaporation process and subsequently thickened to a thick seed metal layer 210 by using a thick electroplating process. This proposed method thus requires two seed metal laying processes, thereby making it an expensive process. Also, the thick seed metal layer 210 needs to be removed by backgrinding/CMP process. A limitation of this proposed method of forming through-wafer vias by performing double seed metal laying processes is that it is suitable only for shallow through-wafer vias (<150 um) with narrow openings (<5 um). This is because it takes a longer time to fill the through-wafer vias by evaporation and electroplating. In cases where larger vias (>5 um) are used, a very thick electroplated metal is formed on one side by the time the via openings are fully closed. The thick metal thus formed induces high stress on the wafer 204 and may cause the wafer 204 to crack. Also the cost of this proposed method is much higher due to double seed layer process and backgrinding or CMP for removing the excess seed metal after electroplating. Additionally, such a method requires the handling of thin wafers by a wafer-bonding machine, which can be a problem since thin wafers have more structural liabilities.
In another article entitled “Through-Wafer Copper Electroplating For 3-Dimensional ICs” by T. Nguyen et al, DIMES Netherlands, Institute Of Physics Publishing, Journal Of Micromechanics And Microengineering, a further method is proposed using wafer-to-wafer bonding with a photoresist layer as a bonding material to form through-wafer vias in a wafer. The wafer with the through-wafer vias is first bonded to another wafer with a seed metal layer using the photoresist layer sandwiched between the seed metal layer and the wafer with the through-wafer vias. The photoresist layer exposed by the through-wafer vias is then subjected to exposure and development through the through-wafer vias to form seed areas. Once the seed areas are formed, electroplating is performed to fill the through-wafer vias using these seed areas. A limitation of this proposed method is the attendant difficulty to perform wafer-to-wafer bonding effectively using the photoresist layer without having enough solvent content to keep the photoresist layer soft. Also, the exposure and development of the seed areas performed through the deep through-wafer vias is not effectively performed as the developer cannot clear the photoresist exposed by through-wafer vias which are deep (>100 um). Even after a very long exposure time (5 min) and after development is performed on the photoresist layer, photoresist residuals are reportedly left in the through-wafer vias. By using an ultrasonic bath during development, the seed areas in large vias (>50×50μm2) may be opened, but damage to the seed metal layer due to ultrasonic force is observed. Additionally, the separation of the bonded wafers is not an easy task as the through-wafer via fill materials in the first wafer are attached to the seed metal layer on the second wafer. Furthermore, if the two wafers are to be separated by a backgrinding process, the two wafers may not have sufficient bond strength to withstand the shear force applied during the backgrinding process since the photoresist layer is not inherently suitable for bonding the two wafers.
From the foregoing problems, it is apparent that there is a need to provide an alternative to the conventional wafer-level packaging for micro-devices.